1) Field of the Invention
This invention relates generally to fabrication of semiconductor devices and more particularly to the formation of spacers on gate structures for Salicide processes For CMOS semiconductor devices.
2) Description of the Prior Art
The Complementary Metal Oxide Semiconductor (CMOS) technology has been recognized as the leading technology for use in digital electronics in general and for use in many computer products in particular. This is because the Integrated Circuits (IC) formed on silicon wafers using CMOS technology have high density, operate at high speed and have a low standby power consumption. Despite these advantages the CMOS technology has been associated with high sheet resistance in the source and drain regions of the transistors as well the polysilicon films frequently used to form the gate regions. This high sheet resistance is detrimental to the basic operations of the CMOS device, such as the speed and power consumption.
Self-aligned silicided (SALICIDE) metal oxide semiconductor techniques are frequently used to reduce the sheet resistance of a CMOS device thereby improving speed characteristics of the device. In this technique, a thin film of metal such as Titanium (Ti), Cobalt (Co) etc., is reacted with the source, drain and Polysilicon regions under specified conditions. The thin film of metal is reacted with the silicon to form a layer of silicide. Thus, titanium is reacted with silicon to form Titanium Silicide (TiSi2). The silicide layer has a lower sheet than the sheet resistance of silicon. During the manufacturing process, a silicide layer when formed at a low temperature prevents the formation of a silicide layer over silicon dioxide or silicon nitride. Further, the unreacted metal film formed over oxide or silicon nitride can be etched using chemicals wet agents without adversely affecting the silicide formed in the polysilicon and silicon regions.
To prevent electrical shorting of adjacent silicide region i.e., the source, gate and drain regions, Prior art processes use oxide (Silicon Dioxide-SiO2) spacers to isolate these regions.
Although this technique shows the advantages of self-aligning and of low resistance of gate and source/drain in MOS technology, many problems still exist because shorter spaces and shallower junctions are needed to properly scale down the devices. If the length of sidewall oxide is to be reduced, isolating the gate and source/drain regions during the silicidation process becomes extremely difficult because of the lateral diffusion of the silicon and the metal along the sidewall oxide. This will result in shorting of gate and source/drain areas. It will be understood that the limit on the length of spacer is dependent on the temperature of metal/silicon reaction and the thickness of the metal film deposited. The problem is especially severe for MOS devices using LDD structures with the self-aligned silicidation of the gate and source/drain regions.
The importance of overcoming the various deficiencies noted above with the bridging and shorting in the salicide process is evidenced by the extensive technological development directed to the subject, as documented by the relevant patent and technical literature. The following patents show various methods for forming double spacers.
U.S. Pat. No. 4,912,061 (Nasr): Method of forming a salicided self-aligned metal oxide semiconductor device using a disposable silicon nitride spacer--shows a double spacers (oxide and nitride)on the sidewalls of a gate. The fabrication of the device is accomplished in seven major steps: First, on a substrate having an oxide layer, an undoped polysilicon layer defining the gate region is deposited. Second, an oxide layer is grown and then a silicon nitride layer is deposited. Third, the oxide and the silicon nitride layers are selectively etched, leaving the oxide and the nitride layers on the walls of the polysilicon gate region. However, this structure does not solve the problem of shorting between the S/D and gate in salicide processes.
U.S. Pat. No. 5,663,586 (Lin) shows an FET device with double spacer.
U.S. Pat. No. 5,208,472 (Su) Double spacer salicide MOS device and method --shows multilayer dielectrics used at the edge of the gate electrode, and the gate electrode, the source and the drain have metal silicide regions.